The present invention relates to the suppression of cross diffusion and/or gate depletion in integrated circuit devices. More particularly, the present invention relates to a scheme for suppressing cross diffusion and gate depletion in a 6T SRAM cell.
Integrated circuit devices commonly employ a laminar or polysilicide structure composed of a polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. In many cases, the polycrystalline silicon film comprises an N+ polysilicon region doped with an N type impurity and a P+ polysilicon region doped with a P type impurity. The present inventors have recognized that many P+ and N+ dopant materials are subject to migration from a given polysilicon layer to another polysilicon layer, to an overlying conductive layer, or to another region of the given polysilicon layer. As a result, these opposite types of impurities are subject to cross diffusion. This cross diffusion can lead to performance degradation in the integrated circuit device.
Accordingly, there is a need for a scheme for suppressing cross diffusion of dopant materials between oppositely doped regions of polysilicon layers in integrated circuit devices.